1. Technical Field
This disclosure relates to a semiconductor device.
2. Description of Related Art
A transistor or opto-coupler electrically insulated between the input side and the output side is commonly known in the prior art as a semiconductor element for use in gate driving of a switching element, such as an IGBT (insulated-gate bipolar transistor), which constitutes a power conversion bridging circuit in an industrial inverter. Furthermore, in recent years, high-voltage ICs (HVICs) in which the input side and the output side are not electrically insulated, have been used, principally in low-capacity inverter applications, in order to lower costs (see, for example, T. Fujihira et al., Proposal of New Interconnection Technique for Very High-Voltage IC's, Japanese Journal of Applied Physics, November 1996, Vol. 35 (First edition), No. 11, pp. 5655-5663).
In order to manufacture a high-voltage IC at low cost, it is suitable to apply an IC process, which enables the use of inexpensive bulk substrates, and employs self-isolation technology that does not require a special element isolation process. Fujihira et al., for example, discloses a high-voltage IC, which is fabricated (manufactured) by this self-isolated IC process. The structure of a high-voltage IC manufactured by the self-insulated IC process will now be described.
FIG. 9 is a plan diagram showing a schematic view of the plan structure of a conventional high-voltage IC. FIG. 10 is a cross-sectional diagram showing a cross-sectional structure along cross-section AA-AA′ in FIG. 9. FIG. 11 is a circuit diagram showing an equivalent circuit of the high-voltage IC in FIG. 10.
As shown in FIG. 9, the high-voltage IC 200 is provided with a high-side drive circuit 210, a level shifter 214, and a control circuit 215. The high-side drive circuit 210 is provided with a gate drive circuit, a level-shift resistance, and the like. The high-side drive circuit 210 is arranged in a high-side region 220. The periphery of the high-side region 220 is surrounded by a high-voltage isolation region 224. The high-side region 220 is electrically isolated from a low-side region 225 by the high-voltage isolation region 224. The level shifter 214 is arranged in the high-voltage isolation region 224. A level-shift resistance 217 is connected between the VB terminal and the level shifter 214 as shown in FIG. 11.
Referring back to FIG. 9, the periphery of the high-voltage isolation region 224 is surrounded by the low-side region 225. A control circuit 215 which controls the high-side drive circuit 210 is arranged in the low-side region 225. The low-side region 225 is the portion apart from the high-side region 220, the high-voltage isolation region 224 and the level shifter 214. The gate drive circuit which forms the high-side drive circuit 210 is includes a CMOS (complementary metal-oxide semiconductor) in which a high-side p-channel MOSFET (p-channel metal-oxide semiconductor field-effect transistor, called “PMOS” below) 212, and an n-channel MOSFET (called “NMOS” below) 213, are connected in complementary fashion as shown in FIG. 11.
In FIG. 10, a high-voltage IC made by a self-isolated IC process, a lateral-type PMOS 212 of the high-side drive circuit 210 is formed in an n diffusion region 202 which is provided selectively on the surface layer of a p−− bulk substrate 201. A p diffusion region 203 is formed to a comparatively shallow depth inside the n diffusion region 202, and a lateral-type NMOS 213 is formed in this p diffusion region 203. The n diffusion region 202 is connected to a VB terminal which is the highest electric potential of the high-side drive circuit 210. The p diffusion region 203 is connected to a VS terminal which is the lowest electric potential of the high-side drive circuit 210. The potential difference between the VB terminal and the VS terminal is the power source voltage of the high-side drive circuit 210, which is approximately 15 V, for example.
A p− region 204 is provided inside the low-side region 225 on the portion of the surface layer of the p−− bulk substrate 201 to the outside of the n diffusion region 202. The p−− bulk substrate 201 and the p− region 204 are connected to a GND terminal at ground potential (0 V, for example). An n− low-concentration diffusion region 205 constituting the high-voltage isolation region 224 is provided between the n diffusion region 202 and the p− region 204. When the potential of the high-side region 220 is raised to a high voltage of 600 V or more above the low-side region 225, then the pn junction between the n− low-concentration diffusion region 205 and the p− region 204 is reverse-biased, whereby the n− low-concentration diffusion region 205 becomes depleted and the voltage resistance in the lateral direction (the direction parallel to the main surface of the substrate) is maintained.
As shown in FIG. 11, the high-voltage IC 200 is connected to a power conversion bridge circuit, for example, and drives a first and a second MOSFET 101, 102, which constitute one phase of the power conversion bridge circuit. The first and second MOSFETs 101, 102 are connected in series between a high-voltage main power source (anode side) Vdc and a ground potential GND which is the cathode side of the main power source. The VS terminal is connected to a contact point 105 between the first MOSFET 101 and the second MOSFET 102. The contact point 105 is the output point of the bridge circuit that is constituted by the first and second MOSFETs 101 and 102. Reference numerals 103 and 104 are FWD (free-wheeling diodes).
The operation of the high-voltage IC 200 is described with reference to an example for driving the first MOSFET 101 on the high side of the power conversion bridge circuit. The high-side drive circuit 210 takes the potential of the contact point 105 where the VS terminal is connected as a reference potential VS and operates at a potential between the reference potential VS and the power source potential VB, which is the highest potential of the high-side drive circuit 210. When a boot-strap circuit is used, the power source potential VB of the high-side drive circuit 210 is higher than the reference potential VS by an amount corresponding to the voltage of the boot-strap capacitor. The control circuit 215 operates by taking the ground potential GND as a reference, and generates an on/off control signal referenced to GND for switching the first MOSFET 101 on and off.
The GND-referenced on/off control signal is converted to an on/off control signal referenced to VS, by the level shifter 214, and is transmitted to the high-side drive circuit 210. The on/off signal input to the high-side drive circuit 210 is input to the gate of the first MOSFET 101 via the gate drive circuit 211. The first MOSFET 101 is switched on and off on the basis of this on/off signal. Due to the first MOSFET 101 switching on and off on the basis of the on/off signal from the control circuit 215 transmitted via the level shifter 214 in this way, the potential of the VS terminal varies from 0 V (GND) to several hundred V (Vdc) in combination with the on/off switching of the second MOSFET 102.
A conventional high-voltage IC of this kind has been proposed in which the size of the device is reduced without increasing manufacturing costs, by setting the high-voltage isolation region between a level-shift n-channel MOSFET and an isolated region to be a region where a p-type substrate region (or p diffusion layer) made from a p-type substrate is exposed on the front surface of the substrate, instead of a p diffusion region and a resurf region peripheral to same as in the prior art (see, for example, Japanese Patent No. 3917211).
In Japanese Patent No. 3917211, the potential difference between n diffusion regions, which are divided by the high-voltage isolation region is used as a signal voltage for level shifting. Therefore, one of the n diffusion regions (isolated regions) which is divided by the high-voltage isolation region is set to the power source potential, and the other n diffusion region is set to the drain potential of the level-shift n-channel MOSFET. The drain potential of the level-shift n-channel MOSFET becomes the power source potential of the high-voltage IC when the level-shift re-channel MOSFET is off, and becomes a potential that is lower than the power source potential by a voltage value obtained by multiplying the level-shift resistance by the current value of the level-shift n-channel MOSFET, when the level-shift re-channel MOSFET is on.
Furthermore, the following device has been proposed as a conventional high-voltage IC. Provided on a p− silicon substrate are: an n− region surrounded by a p− well region, a drain n+ region connected to a drain electrode, a p base region surrounding the drain n+ region and separated from the drain n+ region, and a source n+ region disposed inside the p base region. The n− region is isolated from the first n− region and the second n− region by a p− region which passes through the n− region and reaches the p− silicon substrate. A drain n+ region is provided in the first n− region. The first n− region has a floating potential (see Japanese Translation of PCT Application No. 2012-519371, for example).